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19-1431; Rev 3; 12/01
Direct-Conversion Tuner IC for Digital DBS Applications
General Description
The MAX2104 low-cost direct-conversion tuner IC is designed for use in digital direct-broadcast satellite (DBS) television set-top box units. Its direct-conversion architecture reduces system cost compared to devices with IF-based architectures. The MAX2104 directly converts L-band signals to baseband signals using a broadband I/Q downconverter. The operating frequency range extends from 925MHz to 2175MHz. The IC includes an LNA gain control, I and Q downconverting mixers, lowpass filters with gain control and frequency control, a local oscillator (LO) buffer with a 90 quadrature network, and a charge-pump based PLL for frequency control. The MAX2104 also has an on-chip LO, requiring only an external varactor-tuned LC tank for operation. The output of the LO drives the internal quadrature generator and dual modulus prescaler. An on-chip crystal amplifier drives a reference divider as well as a buffer amplifier to drive off-chip circuitry. The MAX2104 is offered in a 48-pin TQFP-EP package. o Low-Cost Architecture o Operates from Single 5V Supply o 925MHz to 2175MHz Input Frequency Range o On-Chip Quadrature Generator, Dual-Modulus Prescaler (/32, /33) o On-Chip Crystal Amplifier o PLL Mixer with Gain-Controlled Charge Pump o Input Levels: -25dBm to -65dBm per Carrier o Over 40dB Gain Control Range o Noise Figure = 11.5dB; IIP3 = 7dBm (at 1550MHz) o Automatic Baseband Offset Correction o Loopthrough Replaces External Splitter o Crystal Output Buffer
Features
MAX2104
Applications
DirecTV, PrimeStar, EchoStar DBS Tuners DVB-Compliant DBS Tuners Broadband Systems LMDS
PART MAX2104CCM*
Ordering Information
TEMP RANGE 0C to +70C PIN-PACKAGE 48 TQFP-EP
*Contact factory for availability. Functional Diagram appears at end of data sheet.
Pin Configuration
TOP VIEW
CP FB GND VCC TANK+ VRLO TANKGND GND VCC PSOUTPSOUT+
48 47 46 45 44 43 42 41 40 39 38 37
VCC CFLT XTLXTL+ GND VCC RFINRFIN+ GND GND QDCQDC+
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
36 35 34 33 32 31 30 29 28 27 26 25
PLLINPLLIN+ MODMOD+ GND IOUT+ IOUTVCC QOUT+ QOUTFDOUB FLCLK
MAX2104
________________________________________________________________ Maxim Integrated Products
IDCIDC+ GND GND RFOUT CPG1 VCC XTLOUT CPG2 GC1 GC2 INSEL
TQFP
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Direct-Conversion Tuner IC for Digital DBS Applications MAX2104
ABSOLUTE MAXIMUM RATINGS
VCC to GND .............................................................-0.5V to +7V All Other Pins to GND.................................-0.3V to (VCC + 0.3V) RF1+ to RF1-, RF2+ to RF2-, TANK+ to TANK-, IDC+ to IDC-, QDC+ to QDC- ............................................2V IOUT_, QOUT_ to GND Short-Circuit Duration ......................10s PSOUT+, PSOUT- to GND Short-Circuit Duration .................10s Continuous Current (any pin)..............................................20mA Continuous Power Dissipation (TA = +70C) (derate 27mW/C above +70C) .......................................1.5W Operating Temperature Range...............................0C to +85C Junction Temperature ......................................................+150C Storage Temperature Range ............................-65C to +150C Lead Temperature (soldering, 10s) ................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 4.75V to 5.25V, VFB = 2.4V, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RFIN_ = floating, RIOUT_ = RQOUT_ = 10k, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25C. Typical values are at VCC = 5.0V and TA = +25C, unless otherwise noted.) PARAMETER Operating Supply Voltage Operating Supply Current Digital Input Voltage High Digital Input Voltage Low Digital Input Current FLCLK Input Voltage High FLCLK Input Voltage Low FLCLK Input Current (Note 1) Common-Mode Input Voltage Input Voltage Low (Note 2) Input Voltage High (Note 2) Input Current (Note 1) DIFFERENTIAL DIGITAL OUTPUTS (PSOUT+, PSOUT-) Common-Mode Output Voltage Output Voltage Low (Note 3) Output Voltage High (Note 3) FREQUENCY SYNTHESIZER Prescaler Ratio Reference Divider Ratio VCPG1 = VCPG2 = 0.5V Charge-Pump Output High Measured at FB VCPG1 = 0.5V, VCPG2 = 2.4V VCPG1 = 2.4V, VCPG2 = 0.5V VCPG1 = VCPG2 = 2.4V (VMOD+ - VMOD-) = 200mV (VMOD+ - VMOD-) = -200mV 32 33 8 0.08 0.24 0.48 1.44 0.1 0.3 0.6 1.8 32 33 8 0.12 0.36 0.72 2.16 mA VCMO Referenced to VCMO Referenced to VCMO 150 2.16 2.4 -215 215 2.64 -150 V mV mV VCMI Referenced to VCMI Referenced to VCMI 100 -5 5 RSOURCE = 50k, VFLCLK = 1.65V -1 1.08 1.2 DIFFERENTIAL DIGITAL INPUTS (MOD+, MOD-, PLLIN+, PLLIN-) 1.32 -100 V mV mV A SYMBOL VCC ICC VIH VIL IIN -15 1.85 1.45 +1 2.4 0.5 +10 CONDITIONS MIN 4.75 190 TYP MAX 5.25 275 UNITS V mA V V A V V A
STANDARD DIGITAL INPUTS (FDOUB, INSEL, CPG1, CPG2)
SLEW-RATE-LIMITED DIGITAL INPUTS
2
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Direct-Conversion Tuner IC for Digital DBS Applications
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.75V to 5.25V, VFB = 2.4V, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RFIN_ = floating, RIOUT_ = RQOUT_ = 10k, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25C. Typical values are at VCC = 5.0V and TA = +25C, unless otherwise noted.) PARAMETER Charge-Pump Output Low Measured at FB Charge-Pump Output Current Matching Positive to Negative Charge-Pump Output Leakage Charge-Pump Output Current Drive (Note 1) ANALOG CONTROL INPUTS (GC_) Analog Control Input Current Differential Output Voltage Swing Common-Mode Output Voltage (Note 1) Offset Voltage (Note 1) IGC_ VGC_ = 1V to 4V -50 +50 A BASEBAND OUTPUTS (IOUT+, IOUT-, QOUT+, QOUT-) RL = 2k differential 1 0.65 -50 0.85 +50 VP-P V mV SYMBOL CONDITIONS VCPG1 = VCPG2 = 0.5V VCPG1 = 0.5V, VCPG2 = 2.4V VCPG1 = 2.4V, VCPG2 = 0.5V VCPG1 = VCPG2 = 2.4V Measured at FB Measured at FB Measured at CP MIN -0.12 -0.36 -0.72 -2.16 -5 -25 100 TYP -0.1 -0.3 -0.6 -1.8 MAX -0.08 -0.24 -0.48 -1.44 5 25 UNITS
MAX2104
mA
% nA A
AC ELECTRICAL CHARACTERISTICS
(VCC = 4.75V to 5.25V, VIOUT_ = VQOUT_ = 0.59VP-P, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RIOUT_ = RQOUT_ = 10k, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25C. Typical values are at VCC = 5.0V and TA = +25C, unless otherwise noted.)
PARAMETER RF FRONT END RFIN_ Input Frequency Range RFIN_ Input Power for 0.59Vp-p Baseband Levels RFIN_ Input Third-Order Intercept (Note 4) RFIN_ Input Second-Order Intercept (Note 5) Output-Referred 1dB Compression Point (Note 6) Noise Figure IP3RFIN_ fRFIN Single carrier VGC1 = VGC2 = +4V (min gain) VGC1 = VGC2 = +1V (max gain) fLO = 2175MHz 925 -20 -68 5 7 8 15.5 2 dBm dBV dBm -65 2175 MHz dBm dBm SYMBOL CONDITIONS MIN TYP MAX UNITS
PRFIN_ = -25dBm per fLO = 1550MHz tone fLO = 950MHz PRFIN_ = -25dBm per tone, fLO = 951MHz PRFIN_ = -40dBm, signals within filter bandwidth PRFIN_ = -65dBm, fRFIN_ = 1550MHz, VGC1 = 1V, VGC2 adjusted 0.59Vp-p baseband level fRFIN_ = 925MHz fRFIN_ = 2175MHz Average level of VIOUT_, VQOUT_ Average level of VIOUT_, VQOUT_ 27 31
IP2RFIN_ P1dBOUT_
NF
11.5 10 10 38
dB
RFIN_ Return Loss (Note 7) LO 2nd Harmonic Rejection (Note 8) LO Half Harmonic Rejection (Note 9)
dB dBc dBc
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Direct-Conversion Tuner IC for Digital DBS Applications MAX2104
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.75V to 5.25V, VIOUT_ = VQOUT_ = 0.59VP-P, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RIOUT_ = RQOUT_ = 10k, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25C. Typical values are at VCC = 5.0V and TA = +25C, unless otherwise noted.) PARAMETER LO Leakage Power (Notes 7, 10) RFOUT PORT (LOOPTHROUGH) f = 925MHz RFIN_ to RFOUT Gain (Note 11) f = 1550MHz f = 2175MHz f = 925MHz RFOUT Output Third-Order Intercept Point (Note 11) f = 1550MHz f = 2175MHz f = 925MHz RFOUT Noise Figure (Note 11) RFOUT Return Loss (Notes 1, 11) BASEBAND CIRCUITS Output Real Impedance (Note 1) Baseband Highpass Frequency (Note 1) LPF -3dB Cutoff-Frequency Range (Note 1) Baseband Frequency Response (Note 1) LPF -3dB Cutoff-Frequency Accuracy (Note 1) Ratio of In-Filter-Band to Out-of-Filter-Band Noise Quadrature Gain Error Quadrature Phase Error IOUT_, QOUT_ CIDC_ = CQDC_ = 0.22F Controlled by FLCLK signal Deviation from ideal 7th order, Butterworth, up to 0.7 x fC fFLCLK = 0.5MHz, fC = 8MHz fFLCLK = 1.25MHz, fC = 19.3MHz fFLCLK = 2.0625MHz, fC = 31.4MHz fIN_BAND = 100Hz to 22.5MHz, fOUT_BAND = 67.5MHz to 112.5MHz Includes effects from baseband filters, measured at 125kHz baseband Includes effects from baseband filters, measured at 125kHz baseband 8 -0.5 -5.5 -10 -10 19 1.2 4 50 750 33 +0.5 +5.5 +10 +10 dB dB degrees % Hz MHz dB f = 1550MHz f = 2175MHz 925MHz < f < 2175MHz 0.5 1.8 2.5 9 7 4 15 12 11.5 8 dB dB dBm dB SYMBOL CONDITIONS Measured at RFIN_ MIN TYP -66 MAX UNITS dBm
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Direct-Conversion Tuner IC for Digital DBS Applications
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = 4.75V to 5.25V, VIOUT_ = VQOUT_ = 0.59VP-P, CIOUT_ = CQOUT_ = 10pF, fFLCLK = 2MHz, RIOUT_ = RQOUT_ = 10k, VFDOUB = VINSEL = VCPG1 = VCPG2 = 2.4V, VPLLIN+ = VMOD+ = 1.3V, VPLLIN- = VMOD- = 1.1V, TA = +25C. Typical values are at VCC = 5.0V and TA = +25C, unless otherwise noted.) PARAMETER SYNTHESIZER SYNTHESIZER XTLOUT Output Voltage Swing XTLOUT Output Voltage DC Crystal Frequency Range (Note 1) MOD+, MOD- Setup Time (Note 1) MOD+, MOD- Hold Time (Note 1) LOCAL OSCILLATOR LOCAL OSCILLATOR LO Tuning Range (Note 1) At 1kHz offset, fLO = 2175MHz LO Phase Noise (Notes 7, 12) RFIN_ to LO Input Isolation (Note 10) Note 1: Note 2: Note 3: Note 4: At 10kHz offset, fLO = 2175MHz At 100kHz offset, fLO = 2175MHz fRFIN_ = 2150MHz 590 -55 -75 -95 57 dB dBc/Hz 1180 MHz tSUM tHM Figure 1 Figure 1 4 7 0 Load = 10pF | | 10k, fXTLOUT = 6MHz 0.75 1 2 7.26 1.5 VP-P V MHz ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX2104
Minimum and maximum values are guaranteed by design and characterization over supply voltage. With external 100 termination resistor. Driving differential load of 10k || 15pF. Two signals are applied to RFIN_ at fLO - 100MHz and fLO - 199MHz. VGC2 = 1V; VGC1 is set such that the baseband outputs are at 590mVP-P. IM products are measured at baseband outputs but are referred to RF inputs. Note 5: Two signals are applied to RFIN_ at 1200MHz and 2150MHz. VGC2 = 1V, VGC1 is set such that the baseband outputs are at 590mVP-P. IM products are measured at baseband outputs but are referred to RF inputs. Note 6: PRFIN_ = -40dBm so that front end IM contributions are minimized. Note 7: Using L64733/L64734 demo board from LSI Logic. Note 8: Downconverted level, in dBc, of carrier present at fLO x 2, fLO = 1180MHz, fVCO = 590MHz, VFDOUB = 2.4V. Note 9: Downconverted level, in dBc, of carrier present at fO / 2, fLO = 2175MHz, fVCO = 1087.5MHz, VFDOUB = 2.4V. Note 10: Leakage is dominated by board parasitics. Note 11: VCPG1 = VCPG2 = VFDOUB = VINSEL = 0.5V, fFLCLK = 0.5MHz. Note 12: Measured at tuned frequency with PLL locked. All phase noise measurements assume tank components have a Q > 50.
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Direct-Conversion Tuner IC for Digital DBS Applications MAX2104
Pin Description
PIN 1, 6, 19, 29, 39, 45 2 3 4 5, 9, 10, 15, 16, 32, 40, 41, 46 7 8 11 12 13 14 17 18 20 21 22 23 24 25 26 27 28 30 31 33 NAME VCC CFLT XTLXTL+ GND RFINRFIN+ QDCQDC+ IDCIDC+ RFOUT CPG1 XTLOUT CPG2 GC1 GC2 INSEL FLCLK FDOUB QOUTQOUT+ IOUTIOUT+ MOD+ FUNCTION VCC Power-Supply Input. Connect each pin to a +5V 5% low-noise supply. Bypass each VCC pin to the nearest GND with a ceramic chip capacitor. External Bypass for Internal Bias. Bypass this pin with a 0.1F ceramic chip capacitor to GND. Inverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements. Noninverting Input to Crystal Oscillator. Consult crystal manufacturer for circuit loading requirements. Ground. Connect each of these pins to a solid ground plane. Use multiple vias to reduce inductance where possible. RF Inverting Input. Bypass RFIN- with 47pF capacitor in series with a 75 resistor to GND. RF Noninverting Input. Connect to 75 source with a 47pF ceramic chip capacitor. Baseband Offset Correction. Connect a 0.22F ceramic chip capacitor from QDC- to QDC+ (pin 12). Baseband Offset Correction. Connect a 0.22F ceramic chip capacitor from QDC+ to QDC- (pin 11). Baseband Offset Correction. Connect a 0.22F ceramic chip capacitor from IDC- to IDC+ (pin 14). Baseband Offset Correction. Connect a 0.22F ceramic chip capacitor from IDC+ to IDC- (pin 13). Buffered RF Output. Enabled when INSEL is low. Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See the DC Electrical Characteristics section for available gain settings. Buffered Crystal Oscillator Output Charge-Pump Gain Select. High-impedance digital input. Sets the charge-pump output scaling. See the DC Electrical Characteristics section for available gain settings. Gain Control Input for RF Front End. High-impedance analog input, with an input range of 1V to 4V. See the AC Electrical Characteristics section for transfer function. Gain Control Input for Baseband Signals. High-impedance analog input, with an input range of 1V to 4V. See the AC Electrical Characteristics section for transfer function. Loopthrough Mode Enable. High-impedance digital input. Drive low to enable the RFOUT buffer and disable the internal downconverters. Connect to VCC for normal tuner operation. Baseband Filter Cutoff Adjust. Connect to a slew-rate-limited clock source. See the AC Electrical Characteristics section for transfer function. LO Frequency Doubler. High-impedance digital input. Drive high to enable the LO frequency doubler. Drive low to disable the doubling function. Baseband Quadrature Output. Connect to inverting input of high-speed ADC. Baseband Quadrature Output. Connect to noninverting input of high-speed ADC. Baseband In-Phase Output. Connect to inverting input of high-speed ADC. Baseband In-Phase Output. Connect to noninverting input of high-speed ADC. PECL Modulus Control. A PECL high on MOD+ sets the dual-modulus prescaler to divide by 32. A PECL logic low sets the divide ratio to 33. Drive with a differential PECL signal with MOD- (pin 34).
6
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Direct-Conversion Tuner IC for Digital DBS Applications
Pin Description (continued)
PIN 34 35 36 37 38 42 43 44 47 48 NAME MODPLLIN+ PLLINPSOUT+ PSOUTTANKVRLO TANK+ FB CP FUNCTION PECL Modulus Control. A PECL low on MOD- sets the dual-modulus prescaler to divide by 32. A PECL logic high sets the divide ratio to 33. Drive with a differential PECL signal with MOD+ (pin 33). PECL Phase-Locked Loop Input. Drive with a differential PECL signal with PLLIN- (pin 36). PECL Phase-Locked Loop Input. Drive with a differential PECL signal with PLLIN+ (pin 35). PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used with PSOUT- (pin 38). Requires PECL-compatible termination. PECL Prescaler Output. Differential output of the dual-modulus prescaler. Used with PSOUT+ (pin 37). Requires PECL-compatible termination. LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning. LO Internal Regulator. Bypass with a 100pF ceramic chip capacitor to GND. LO Tank Oscillator Input. Connect to an external LC tank with varactor tuning. Feedback Output. Control of external charge-pump transistor. Voltage Drive Output. Control of external charge-pump transistor.
MAX2104
MOD+, MOD-
50%
50%
tSUM PSOUT+ PSOUT-
tHM 50% 50%
Figure 1. Timing Diagram
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Direct-Conversion Tuner IC for Digital DBS Applications MAX2104
Functional Diagram
CPG1 CPG2 PLLIN+ PLLINXTL+ XTLMOD+ MODFDOUB TANK+ x2 TANKVCC VRLO CFLT GND RFINRFIN+ GC1 GC2 FLCLK 0/90 VOLTAGE REGULATOR /32, 33 /8
MAX2104 CHARGE PUMP CP FB XTLOUT
PSOUT+ PSOUTBASEBAND OFFSET CORRECTION IDC+ IDCQDC+ QDCIOUT+ IOUT-
QOUT+ QOUT-
RFOUT INSEL
8
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Direct-Conversion Tuner IC for Digital DBS Applications
Package Information
32L/48L,TQFP.EPS
MAX2104
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
9 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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